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11-263 product description ordering information typical applications features functional block diagram rf micro devices, inc. 7628 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com optimum technology matching? applied si bjt gaas mesfet gaas hbt si bi-cmos sige hbt si cmos ingap/hbt gan hemt sige bi-cmos rx i i byp rx q q byp vcc bb tx i tx q if in+ if in- vcc if if out+ if out- tx vgc rf out rf in lna gs mode1 mode0 mclk vcc pll4 sdi r bias vcc rf2 vcc rf1 vcc rf3 vcc pll1 pll reg dig reg vref rx vgc sclk ssb 3rd order bes lpf 3rd order bes lpf 3rd order bes lpf 3rd order bes lpf if synth analog rf pll voltage regulator rx if voltage regulator 1 rx if voltage regulator 2 d/a mux lc trap rf synth analog rf pll voltage regulator digital voltage regulator spi serial port frac-n digital p & r 11 31 30 29 28 27 26 25 1 32 2 3 6 7 8 5 4 12 13 14 15 16 22 23 24 17 21 20 19 18 9 10 rf2958 2.4ghz spread-spectrum transceiver ? ieee 802.11b wlans ? wireless residential gateways ? secure communication links ? high speed digital links ? wireless security ? digital cordless telephones the rf2958 is a single-chip transceiver specifically designed for ieee 802.11b applications. the part includes all required transceiver functions. the receiver includes: an lna and downconverter; complete synthe- sizers and vco?s; direct conversion from if receiver with variable gain control; quadrature demodulator; i/q base- band amplifiers; and, on-chip baseband filters. for the transmit side, a qpsk modulator and upconverter are provided along with the synthesizer, vco, and pa driver. a minimum number of external components are required, resulting in an ultra-compact low-cost radio design. two- cell or regulated three-cell (3 .6v maximum) battery appli- cations are supported by the part. the rf2958 is also part of a 2.4ghz chipset along with our high-efficiency gaas hbt pa and the rf3002 baseband processor. ? complete ieee802.11b transceiver including vcos ? small 32-pin leadless package ? minimal external components required ? low receive current ? high performance super-het architecture rf2958 2.4ghz spread-spectrum transceiver rf2958tr13 2.4ghz spread-spectrum transceiver (tape & reel) rf2958 pcba fully assembled evaluation board 0 rev a0 050209 5.000 0.050 5.000 0.050 seating plane scale: none 0.080 c 0.025 0.010 0.100 c m -c- 0.900 0.070 3.400 0.400 0.050 typ 0.500 typ 3.400 shaded lead is pin 1. dimensions in mm. package style: qfn, 32-pin, 5x5 9
11-264 rf2958 rev a0 050209 absolute maximum ratings parameter rating unit supply voltage -0.5 to +3.6 v dc control voltages -0.5 to +3.6 v dc input rf level +12 dbm operating ambient temperature -40 to +85 c storage temperature -40 to +150 c parameter specification unit condition min. typ. max. receiver lna/rf v cc =3.0v, t=+25c, mclk=44mhz, unless otherwise specified rf frequency range 2400 2500 mhz if frequency range 363 385 mhz 374mhz 11mhz voltage gain - high 32 (20db power) 35 (23db power) 38 (26db power) db lna/mixer voltage gain (note: into output impedance). lna/mixer/saw filter voltage gain. lna gs=1 voltage gain - low -1 (-13db power) +2 (-10db power) +5 (-7db power) db lna/mixer voltage gain. lna gs=0 noise figure - high gain 4 dbm noise figure - low gain 32 dbm input ip3 - high gain -23 dbm input ip3 - low gain +8 dbm input p1db - high gain -30 dbm input p1db - low gain -2 dbm input return loss 10 db z 0 =50 ? output impedance 750 ? image rejection 30 db receiver if vga/baseband if frequency range 374 mhz if input impedance 750 ? voltage gain - high 70 db v gc =1.25v (measured to single-ended out- put) voltage gain - low 4 db v gc =1.95v (measured to single-ended out- put) gain accuracy 3 db for a given rx vgc voltage, the measured gain should lie within 3db of ideal gain response time 300 ns measured with a dc step from 1.3v to 1.8v to 90% final value (within 1db) gain flatness -0.25 +0.25 db 374mhz 11mhz, relative to gain at 374mhz input referred noise 11 uv rms measured into the if vga pin. input v1db 500 mv p-p 1db compression of if strip. output distortion 1.0 % measured at input to rf3002 single-ended. output voltage 0.75 v p-p single-ended. output v1db 1.25 v p-p caution! esd sensitive device. rf micro devices believes the furnished information is correct and accurate at the time of this printing. however, rf micro devices reserves the right to make changes to its products without notice. rf micro devices does not assume responsibility for the use of the described product(s). refer to ?handling of psop and pssop products? on page 16-15 for special handling information. refer to ?soldering specifications? on page 16-13 for special solder- ing information.
11-265 rf2958 rev a0 050209 parameter specification unit condition min. typ. max. receiver if vga/baseband, cont?d group delay 15 ns filter rejection db transfer function - 3 pole bessel at 9mhz output impedance 20 ? f<1mhz i/q magnitude error 0.35 db i/q phase error 3.0 i/q dc offset 10 mv s qrt [(v outi -v ref )^2+(v outq -v ref )^2)] dc step 40 mv vgc step 1.3v to 1.8v, p in =-50dbm v ref 1.65 1.7 1.75 v 3% variation v ref output current 1.0 ma source transmitter modulator/baseband i/q magnitude error 0.35 db i/q phase error 3.0 input signal (single-ended) 200 mv p-p input signal magnitude 282 mv p-p sqrt(i^2+q^2) input p1db 566 mv p-p 6db from input voltage gain to if 4 6 8 db measure from complex magnitude to ifv p-p output voltage 448 564 710 mv p-p output snr 32 db connected to saw filter carrier leakage -20 dbc single sideband modulation vga driver/upconverter input p1db 550 mv p-p 6db from max input input referred noise 20 uv rms measured in 11mhz bandwidth at 2.442ghz upconverter gain >12db minimum gain 0 db tx vgc at 1.3v maximum gain 17 db tx vgc at 1.9v gain response time 300 ns measured with 300mv change in gain on txvgc to 90% of final p out . image rejection 30 db rf lo leakage -25 -36 dbm f lo =2048mhz to 2110mhz output voltage 1000 mv p-p 802.11b output with 7db to 20db gain (needed for +20dbm p out ). minimum output power -12 dbm txvgc at 1.3v maximum output power 0 dbm meeting 802.11b spectral mask
11-266 rf2958 rev a0 050209 parameter specification unit condition min. typ. max. digital input specifications apply to pins: ssb, sdi, sclk, mode0, mode1 input high voltage (v ih )0.7v dd v input low voltage (v il )0.3v dd v input high static current (i ih )5 a input low static current (i il )5 a reset time 50 s exiting reset mode or using spi reset apply to pins: ssb, sdi, sclk input setup time (t su )* 5 ns input hold time (t hld )* 5 ns input rise/fall time (t rfi )5ns input clock to select time (t cs )5 ns input clock pulse width high (t cwh ) 22 ns input clock pulse width low (t cwl ) 22 ns pll recalibration pulse width (t rc ) 1/fr s for fr=22mhz, t rc is 45.5ns minimum digital driver output apply to pin: sdi (output mode) output high voltage (v oh )0.8v dd v with 1ma load output low voltage (v ol )0.2v dd v with 1ma load output rise/fall time (t rfo ) 5 ns with 20pf maximum load capacitance mea- sured from 10% to 90% of output voltage output current source (|i oh |) 3.8 ma output at (v dd -0.3v) output current sink (|i ol |) 10 ma output at 0.3v mclk input (ac-coupled) mclk can be driven dc-coupled by a cmos clock oscillator with rail-to-rail out- puts. other oscillator configurations may require ac-coupling. apply to pin: mclk peak-to-peak input voltage (v p-p ) 500 mv dc bias at mclk (mclk_dc) 0.6 1.1 v specification valid range temperature -30 +70 c supply voltage 2.7 3.0 3.6 v transmit current 50 68 80 ma mode0=0, mode1=1 receive current 30 52 60 ma mode0=1, mode1=0 idle current 5 28 40 ma mode0=0, mode1=0 reset current 1 2 ma mode0=1, mode1=1 hibernate current 0.2 0.5 ma *setup and hold times are measured from the time where the waveforms cross vdd/2.
11-267 rf2958 rev a0 050209 digital timing specifications ssb sclk t cs t cwh t cwl sdi msb lsb t su t hld internal recal pulse t rc
11-268 rf2958 rev a0 050209 pin function description 1if in+ differential input from if saw filter. see application schematic for matching circuit. 2if in- see pin 1. 3 vcc if power supply for if circuitry. provide 330pf bypass capacitor close to this pin. 4r bias bandgap voltage reference for on-chip biasing. install a 22.1k ? , 1% resistor from this pin to ground. 5 vcc rf2 power supply for tx and rx bias, lo buffers and mixers. provide 6pf bypass capacitor close to this pin. 6 vcc rf1 see pin 5. 7if out- differential output to if saw filter. see application schematic for matching circuit. 8 if out+ see pin 7. 9tx vgc tx analog gain control. depending on desired operation mode, transmitter gain can be controlled through this pin or the three-wire digital interface. this pin can also provide a bias voltage to an external pa. see theory of operation for details. 10 rf out tx pa driver output. 11 vcc rf3 power supply for lna and tx output driver. power should be connected to this pin through an inductor or a long 50 ? transmission line rf-shorted with a 6pf capacitor at the other end. 12 rf in rx input from antenna. 13 lna gs gain select pin for the internal lna. high-gain operation is selected when this pin is a logic ?1?. 14 vcc pll1 power supply for the pll rf lo synthesizer. provide 0.01 f and 6pf bypass capacitors close to this pin. 15 pll reg internal pll regulator output. bypass wi th 10nf capacitor. do not connect to v cc or ground. 16 mode1 controls operational state of the device. see theory of operation section for details. 17 mode0 see pin 16. 18 mclk reference oscillator for the pll synthesizer. 19 sdi data signal for the synchronous three-wire digital control interface. 20 ssb chip select signal for the synchronous three-wire digital control interface. 21 sclk clock signal for the synchronous three-wire digital control interface. 22 vcc pll4 power supply for the pll if lo synthesizer. provide 0.01 f and 330pf bypass capacitors close to this pin. 23 dig reg internal digital regulator output. bypass wi th 10nf capacitor. do not connect to v cc or ground. 24 vref i/q dc reference voltage for the baseband processor. this pin should be connected to a high impedance on the baseband processor. 25 q byp baseband differential input signal for the tx quadrature channel. for single-ended applications, bypass to ground with a 0.01 f capacitor. 26 tx q baseband input signal for the tx quadrature channel. 27 i byp baseband differential input signal for the tx in-phase channel. for single-ended applications, bypass to ground with a 0.01 f capacitor. 28 tx i baseband input signal for the tx in-phase channel. 29 vcc bb power supply for baseband circuitry. provide 0.01 f bypass capacitor close to this pin. 30 rx q baseband output signal for the rx quadrature channel. 31 rx i baseband output signal for the rx in-phase channel. 32 rx vgc analog gain control for the rf if amplifier. pkg base gnd device ground. connect directly to pcb ground plane. esd all pins except pin 12 are provided with electrostatic discharge protection to 3kv using the human body model.
11-269 rf2958 rev a0 050209 pin out rx vgc 32 rx i 31 rx q 30 29 vcc bb vref 24 tx i 28 i byp 27 r bias 4 5 if in+ 1 if in- 2 vcc if 3 vcc rf1 6 if out- 7 if out+ 8 9 tx vgc 10 11 rf in 12 13 lna gs 14 vcc pll1 15 pll reg 16 mode1 mode0 17 mclk 18 21 vcc pll4 22 sdi 19 sclk 20 dig reg 23 q byp 25 tx q 26 vcc rf2 ssb vcc rf3 rf out
11-270 rf2958 rev a0 050209 detailed functional block diagram rx i i byp rx q q byp vcc bb tx i tx q if in+ if in- vcc if if out+ if out- tx vgc rf out rf in lna gs mode1 mode0 mclk vcc pll4 sdi r bias vcc rf2 vcc rf1 vcc rf3 vcc pll1 pll reg dig reg vref rx vgc sclk ssb 3rd order bes lpf 3rd order bes lpf 3rd order bes lpf 3rd order bes lpf if synth analog rf pll voltage regulator rx if voltage regulator 1 rx if voltage regulator 2 d/a mux lc trap rf synth analog rf pll voltage regulator digital voltage regulator spi serial port frac-n digital p & r 11 31 30 29 28 27 26 25 1 32 2 3 6 7 8 5 4 12 13 14 15 16 22 23 24 17 21 20 19 18 9 10
11-271 rf2958 rev a0 050209 theory of operation the rf2958 is a single-chip transceiver designed specifically for ieee 802.11b wi reless lan applications. in addition to typical transceiver functions of rf conversion of both the transmit and receive signals, the rf2958 incorporates a low- noise amplifier (lna) and a dual phase-locked loop (pll) frequency synthesizer to reduce end-product component count and to simplify integration into end-products. the rf2958 uses a superheterodyne frequency conversion architec- ture in both the transmit and receive signal paths for superior performance in 802.11b applications. it also incorporates power conservation functionality to increase battery life in portable and mobile applications. when used with the rf3002 baseband processor and rf5189 power amplifier (pa), the rf2958 is part of a complete phy solution for 802.11b appli- cations (see figure belo w, 2.4ghz ieee 802.11b chipset block diagram). system architecture the overall system architecture is based around a superheterodyne conversion process. for the transmitter side, the baseband in-phase (i) and quadrature (q) signal components are converted to an intermediate frequency (if) of 374mhz. an external saw filter is used to filter out undesired spurious frequencies. the if is then converted to the over- the-air radio frequency (rf) between 2.412ghz and 2.483ghz using low-side injection. the rf output drives a pa to amplify the signal to the desired power level at the antenna. generally the pa is followed by a tx/rx switch and a band pass filter which eliminates the undesired sideband resultin g from the mixing process before broadcasting the signal through the antenna. the receiver is the inverse of this process. the signal from the antenna passes through the band pass filter, which is in this case acting as a pre-selection filter. the received signal passes through the integrated lna and is converted to an if of 374mhz. the signal then passes through a saw filter, which acts to reject adjacent channels as defined by the 802.11 standard. due to the bandwidth of this filter, adjacent channels must be at least 20mhz apart. the filtered if sig- nal is then downconverted to baseband i and q components. the local oscillato rs required by the mixing proces s are generated by internal if and rf pll frequency synthesizers. these are controlled through a three-wire serial data interface. rf2958 sdi f c = 374 mhz bw = 20 mhz if pll rf pll serial data interface pll/power control registers ref tx vgc rx vgc rf3002 cca rx vgc 802.11 preamble/ header 802.11 preamble/ header control port rxvgc dac q in adc tx vgc dac i out dac q out dac modulator mode control tx length tx signal service demodulator i in adc data converter reference ant sel rx i vref rx q tx i tx q m clk tx pe rx pe tx data tx rdy spi rx rdy rx data cca lna gs data clk tx/rx switch f c = 2450 mhz bw = 100 mhz antenna diversity switch tx pe rx pe rf5189
11-272 rf2958 rev a0 050209 general application information this part is used at high frequencies. proper attention to layout and component selection is critical in order to achieve the specified performance. values for dc blocking capacitors and power supply bypass capacitors should be selected so that they are series self-resonant at the frequency of operat ion. in addition, transmission line techniques should always be used on signal lines at rf frequencies, and may be requir ed on signal lines at if frequencies if connections are long with respect to wavelength. the rf2958 should be powered fr om regulated supply. if not sharing this supply with the mclk oscillator, the mclk oscillator should also be powered from a well-regulated supply. avoid sharing the rf2958 and mclk oscillator supplies with the baseband processor and/or mac. power supply bypassing of vcc lines for the pll is critical in order to minimize the effects of power supply noise on phase noise performance. in addition to rf/if bypassing, these lines should be bypassed with low-frequency capacitors. a value of 0.01 f is sufficient for most applications, but performance should be verified by looking at a modulated signal on a vector signal analyzer or a constant signal on a spectrum analyzer or phase noise test set. since this is a mixed-signal device, care should be taken to separate traces connecting to digital circuits from those con- necting to analog circuits. power supply bypassing is important to keep the noise contributions of digital circuits to a min- imum. it is generally better to start with more bypassing than you think you need, then remove components and re- evaluate performance. enable/disable modes operation of the device is controlled by the mode0 and mode1 pins according to the following truth table. when switching between modes, ensure that mode0 and mode1 are high for less than three master clock cycles to avoid inadvertently entering reset modes. to enter reset mode, ensure that mode0 and mode1 are high for at least five master clock cycles. in idle mode, the if and rf plls are locked and the baseband circuitry is powered; everything else is disabled. in reset mode, the voltage regulators for the digital circuitry inside the part are enabled; everything else is disabled. additionally, there is a hibernate mode in which everything is disabled. this mode is entered by writing the value 8h to register 0 while in hibernate mode. the mode0 and mode1 pins should be held high while in hibernate mode. to exit this mode, toggle the states of one or both mode pins. all registers will need to be reprogrammed on exiting hibernate mode. receiver front end lna/mixer the lna/mixer provides 35db conversion gain to if in high-ga in mode to detect weak signals at the antenna. in low-gain mode, the lna/mixer provides 2db conversion gain. the lna gs pin selects gain mode. when lna gs is high, the part is in high-gain mode. the mixer output is connected to the if out pins as a differential signal for connecting to an exter- nal saw filter. proper matching at the input and output of the saw filter is essential for maintaining performance through the system. the if input and output differential impedances are 750 ? nominal. the same filter is used for transmitter and receiver. internal switches control which signal is present at the saw filter. if ac-coupling is required for the saw filter , use values less than 150pf to ensure that switching sp eed will not be seri- ously degraded. mode0 mode1 function 00idle 0 1 transmit enable 1 0 receive enable 11reset
11-273 rf2958 rev a0 050209 if/baseband the filtered if signal is processed through a variable gain amplifier controlled through the rx vgc pin. the if signal is then downconverted to baseband i and q signals, which are then filtered on-chip with third order bessel filters. the if-to-baseband conversion gain range is 4db to 72db depen ding on the voltage present on the rx vgc pin. the gain slope is negative over a range of 1.2v to 2.0v. the single-ended i and q outputs should be dc-coupled to the baseband processor. the dc reference voltage should be provided to the baseband processor through the vref pin to eliminate the potential for a signal blocker at dc. transmitter the i and q inputs are differential. to use single-ended inputs, place 0.01 f capacitors at the i byp and q byp pins. the inputs should be dc-coupled from the baseband processor. in order to improve carrier suppression at rf, the dc reference voltage should be provided to the baseband processor through the vref pin. the baseband input signals are filtered on-chip using third order bessel filters for spectral shaping. the signals are then complex upconverted to if. the if mixer output is amplified and connected to the if out pins as a differential signal for connecting to the external saw filter as described above. the differential signal from the saw filter is then amplified us ing a variable gain amplifier. the gain of this amplifier can be controlled either through the analog tx vgc pin or digitally from the baseband processor or mac, depending on application. the signal is then upconverted to the desired rf output frequency and amplified to a level appropriate to drive a pa to the desired output level at the antenna. in order to further extend battery life, the tx vgc pin can be used to control the bias of the external pa. if the user of the end-product determines that he/she does not require full output power, the pa bias and the gain of the if variable gain amplifier can be controlled by the rf2958 to reduce the current consumption of the pa, thereby increasing battery life. contact rfmd applications engineering for guidance on implementing this feature. dual frequency synthesizer if lo pll the if pll is an integer-n pll nominally programmed to a center frequency of 748mhz. this frequency is divided by two at the if converter. a 44mhz oscilla tor is required to provide the pll re ference frequency through the mclk pin. see the register details and se rial data interface sections for details on programming. rf lo pll the rf lo pll is a fractional-n pll programmed to an appropriate frequency to convert the 374mhz if to the desired rf channel. the nominal step size is 22mhz with a fractional modulus of 2 24 . the 44mhz reference frequency is divided to the appropriate step size. see the register details and serial data interface sections for details on programming. note: to ensure proper operation of the plls, program register 12 [17:16] to ?11b?. all other bits in register 12 should be set to ?0?.
11-274 rf2958 rev a0 050209 serial data interface a three wire serial data interface allows user programming of the internal control registers in the rf2958. the serial data interface consists of the serial select (ssb), serial data in (sdi) and serial clock (sclk) pins. the sdi is a bi-directional pin, by default it is configured as an input to the serial interface, but during a read session it is used as an output. the first bit in a serial transfer (the msb) is the read/write (r/w) bit. r/w = 1 for a read, and r/w = 0 for a write. the figure below shows a timing diagram for a serial transfer to the rf2958 serial data interface. the serial select (ssb) pin is normally high. a serial transfer is initiated by taking ssb low. the address and data bits on the serial data in (sdi) pin are shifted in on rising edges of the serial clock (sclk) pin, msb first. the data is latched and changes take effect on the falling edge of the clock pulse corresponding to the last (18 th ) data bit in the addressed register. if the transfer is inter- rupted, such that the 18 th data bit clock pulse does not occur, th en no data is written to the register. when the synthesizers are programmed, an internal pulse is generated alerting the synt hesizer that a new setting is required. in or der to guarantee that this internal pulse is long enough, the time betwee n the falling edge of the last serial clock pulse and the rising edge of ssb must be at least 1/fr. the rf2958 can be reset to its power on condition (including register defaults) by writing ?011111b? plus 18 don?t care bits to the serial data interf ace. the reset is actually performed when the ssb is raised after the writ e. although this com- mand can be performed during any settings of the mode0 and mode1 pins, care should be taken to ensure that the registers are reprogrammed in a sufficient time to perform any transmit or receive operations. rw=1 addr4 addr3 addr1 addr0 data17 data16 data1 data0 serial write serial read sdi pin direction - input sdi pin direction - output addr4 addr3 addr1 addr0 data17 data16 data1 data0 rw=0 ssb sdi sclk ssb sclk sdi
11-275 rf2958 rev a0 050209 register details the individual registers and bits are described below. a write instruction to address 11111 causes global reset. all pro- gramming values are binary unless otherwise specified. configuration register 1 (cfg1)-address 00000 if pll register 1 (i fpll1)-address 00001 location bit name default function cfg1(17:16) reserved 00 reserved, program to zero (0) cfg1(15:14) ref_sel(1:0) 00 reference divider value 0 0 divide by 2 1/2 high, 1/2 low 0 1 divide by 3 1/3 high, 2/3 low 1 0 divide by 44 1/44 high, 43/44 low 1 1 divide by 1 (bypass) cfg1(3) hybernate 0 sleep mode current 0=nominal sleep mode current 1=very low sleep mode current cfg1(2) rf_vco_ reg_en 1 rf vco regulator enable 0=disabled 1=enabled cfg1(1) if_vco_ reg_en 1 if vco regulator enable 0=disabled 1=enabled cfg1(0) if_vga_ reg_en 1 if vga regulator enable 0=disabled 1=enabled location bit name default function ifpll1(17) pll_en1 0 if pll enable 0=disabled 1=enabled ifpll1(16) kv_en1 0 if pll kv calibration enable 0=disabled 1=enabled ifpll1(15) vtc_en1 1 if pll coarse tune enable 0=vco coarse tuning system is disabled 1=vco coarse tuning system is enabled ifpll1(14) lpf1 0 if pll loop filter bypass 0=internal loop filter is used 1=internal loop filter is bypassed and external loop filter is used ifpll1(13) cpl1 0 if pll charge pump leakage current 0=minimum value 1=2xminimum value ifpll1(12) pdp1 1 if pll phase detector polarity 0=positive, vco frequency increases with increasing tuning voltage 1=negative, vco frequency decreases with increasing tuning voltage ifpll1(11) autocal_ en1 0 if pll auto calibration enable 0=disabled 1=enabled ifpll1(10) ld_en1 0 if pll lock detect enable 0=disabled 1=enabled ifpll1(9) p1 0 if pll prescaler modulus 0=4/5 mode 1=8/9 mode ifpll1(8:4) reserved 00000 reserved, program to zero (0) ifpll1(3:0) dac1(3:0) 3h if vco coarse tuning voltage lpf_v1=int (coarse tuning voltage/v dd )x16
11-276 rf2958 rev a0 050209 if pll register 2 (i fpll2)-address 00010 if pll register 3 (i fpll3)-address 00011 rf pll register 4 (r fpll1)-address 00100 rf pll register 5 (r fpll2)-address 00101 rf pll register 6 (r fpll3)-address 00110 location bit name default function ifpll2(17:16) reserved 0 reserved, program to zero (0) ifpll2(15:0) if_n(15:0) 22h ifpll divide-by-n value location bit name default function ifpll3(17) reserved 0 reserved, program to zero (0) ifpll3(16:8) dn1(16:8) 1ffh if vco kv calibration, delta n value (signed 2?s complement) deltaf=dn1/(fr) ifpll3(7:4) ct_def1(3:0) 7h if vco coarse tuning value ifpll3(3:0) kv_def1(3:0) 8h if vco kv calibration, default value location bit name default function rfpll1(17) pll_en 0 rf pll enable 0=disabled 1=enabled rfpll1(16) kv_en 0 rf pll kv calibration enable 0=disabled 1=enabled rfpll1(15) vtc_en 1 rf pll coarse tune enable 0=vco coarse tuning system is disabled 1=vco coarse tuning system is enabled rfpll1(14) lpf 0 rf pll loop filter bypass 0=internal loop filter is used 1=internal loop filter is bypassed and external loop filter is used rfpll1(13) cpl 0 rf pll charge pump leakage current 0=minimum value 1=2xminimum value rfpll1(12) pdp 1 rf pll phase detector polarity 0=positive, vco frequency increases with increasing tuning voltage 1=negative, vco frequency decreases with increasing tuning voltage rfpll1(11) autocal_en 0 rf pll auto calibration enable 0=disabled 1=enabled rfpll1(10) ld_en 0 rf pll lock detect enable 0=disabled 1=enabled rfpll1(9) p 0 rf pll prescaler modulus 0=8/9 mode 1=8/10 mode rfpll1(8:4) reserved 00000 reserved, program to zero (0) rfpll1(3:0) dac(3:0) 3h rf vco coarse tuning voltage lpf_v1=int (coarse tuning voltage/v dd )x16 location bit name default function rfpll2(17:6) n2(11:0) 5eh rf pll divide by n value rfpll2(5:0) num2(23:18) 0 rf pll numerator value location bit name default function rfpll3(17:0) num2(17:0) 0 rf pll numerator value
11-277 rf2958 rev a0 050209 rf pll register 7 (r fpll4)-address 00111 calibration register 8 (cal1)-address 01000 txrx register 9 (txrx1)-address 01001 location bit name default function rfpll4(17) reserved 0 reserved, program to zero (0) rfpll4(16:8) dn(8:0) 145 h rf vco kv calibration, delta n value (signed 2?s complement) dn=(deltaf/fr)*256 rfpll4(7:4) ct_def(3:0) 7h rf vco coarse tuning value rfpll4(3:0) kv_def(3:0) 8h rf vco kv calibration, default value location bit name default function cal1(17:13) tvco(4:0) 0fh vco1 warm-up time tvco1=(approximate wa rm-up time)x(fr/32) cal1(12:8) tlock(4:0) 07h vco1 tuning gain calibration, approximate lock time tlock1=(approximate lock time)x(fr/128) cal1(7:3) m_ct_value (4:0) 08h vco1 coarse tune calibration reference clock averaging time m_ct_value=(averaging time)x(fr/32) cal1(2:0) ld_window (2:0) 2h lock detect resolution 0 through 7 location bit name default function txrx1(17) rxdcfbbyps 0 receiver dc removal loop 0=enable dc removal loop 1=disable dc removal loop txrx1(16:15) pcontrol (1:0) 00 00 external txvgc controls vga 01 external txvgc controls vga 10 internal control of vga from register txvgc(4:0) 11 internal control of vga from power control txrx1(14:10) txvgc(4:0) 00000 transmit variable gain select 0h-1fh high gain to low gain txrx1(9:7) rxlpfbw (2:0) 010 receive baseband low pass filter bandwidth selection 000=wide bandwidth 111=narrow bandwidth txrx1(6:4) txlpfbw (2:0) 010 transmit baseband low pass filter bandwidth selection 000=wide bandwidth 111=narrow bandwidth txrx1(3) txdiffmode 0 switches between single-ended and differential mode 0=single-ended mode 1=differential mode txrx1(2) txenmode 0 input buffer enable tx 0=input buffer controlled by txen 1=input buffer controlled by bben txrx1(1) intbiasen 0 internal bias enable 0=disabled - external bias required 1=enabled - internal bias enabled txrx1(0) txbypass 0 tx baseband filters bypass 0=not bypassed 1=bypassed
11-278 rf2958 rev a0 050209 power control register 10 (pcnt1)-address 01010 power control register 11 (pcnt2)-address 01011 vcot1 register 1 (vcot1)-address 01100 test register 1 (test)-address 11011 this is a test register for internal use only. location bit name default function pcnt1(17:15) mid_bias(2:0) 000 used to setup the voltage provided by the pa_bias amplifier to deter- mine the bias voltage to provide to the pa when the desired output power is mid_power. the mid_bias selection will select a v out on pbias between 1.6v and 2.6v. pcnt1(14:9) p_desired (5:0) 000000 user selectable desired output power at antenna. the 5 msb?s are integer portion in dbm. the lsb is 0.5dbm. example: +19.5dbm is represented by 100111. pcnt1(8:3) pc_offset (5:0) 000000 user programmable offset to adjust to process/board variations in the power control loop. this is a 2?s-complement value with the lsb equal to 0.5db. pcnt1(2:0) tx_delay (2:0) 000 user programmable delay to allow a single tx_pe line to be used to enable the bbp and the radio function. programmable in 0.5us increments from 0us to 3.5us. location bit name default function pcnt2(17:12) max_power (5:0) 000000 user programmable max output power provided when pabias=2.6v. this allows the power control function to be customized for various pa?s. the 5 msb?s are integer portion in dbm. the lsb is 0.5dbm. pcnt2(11:6) mid_power (5:0) 000000 user programmable max output power provided when pabias=mid_bias. this allows the power control function to be custom- ized for various pa?s. the 5 msb?s are integer portion in dbm. the lsb is 0.5dbm. pcnt2(5:0) min_power (5:0) 000000 user programmable max output power provided when pabias=1.6v. this allows the power control function to be customized for various pa?s. the 5 msb?s are integer portion in dbm. the lsb is 0.5dbm. location bit name default function vcot1(17) aux 0 if vco band current compensation 0=disabled 1=enabled vcot1(16) aux1 0 rf vco band current compensation 0=disabled 1=enabled vcot1(15:0) reserved 0 reserved, program to zero (0)
11-279 rf2958 rev a0 050209 tx/rx baseband filter response -40 -35 -30 -25 -20 -15 -10 -5 0 5 1.00e+00 1.00e+01 1.00e+02 frequency (mhz) voltage gain (db) 000 001 010 011 100 101 110 111 demodulator gain versus rxvgc versus temperature -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 rxvgc (v) demodulator gain (db) demodulator gain vs. rxvgc @ -30c demodulator gain vs. rxvgc @ 25c demodulator gain vs. rxvgc @ 70c demodulator input v1db versus gain versus temperature 0.1 1.0 10.0 100.0 1000.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 demodulator voltage gain (db) input voltage (mv p-p ) iv1db vs. gain @ -30c iv1db vs. gain @ 25c iv1db vs. gain @ 70c output v1db versus gain versus temperature 100.0 1000.0 10000.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 demodulator voltage gain (db) output v1db (mv p-p ) ov1db vs. gain @ -30c ov1db vs. gain @ 25c ov1db vs. gain @ 70c demodulator magnitude and phase error -2.00 -1.80 -1.60 -1.40 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 baseband frequency (hz) i/q phase error () -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 i/q magnitude error (db) phase error vs. frequency magnitude error vs. frequency
11-280 rf2958 rev a0 050209 upconverter gain versus digital txvgc -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 txvgc value voltage gain (db) upconverter gain vs. txvgc @ -30c upconverter gain vs. txvgc @ 25c upconverter gain vs. txvgc @ 70c upconverter p1db versus analog txvgc -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 txvgc (v) output p1db (dbm) upconverter output p1db vs. txvgc @ -30c upconverter output p1db vs. txvgc @ 25c upconverter output p1db vs. txvgc @ 70c upconverter p1db versus digital txvgc -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 txvgc value output p1db (dbm) upconverter output p1db vs. txvgc @ -30c upconverter output p1db vs. txvgc @ 25c upconverter output p1db vs. txvgc @ 70c modulator magnitude error and image suppression 31.50 32.00 32.50 33.00 33.50 34.00 34.50 35.00 35.50 36.00 36.50 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 baseband frequency (mhz) image suppression (db) -0.15 -0.10 -0.05 0.00 0.05 0.10 i/q magnitude error (db) image suprression vs. frequency magnitude error vs. frequency upconverter gain versus analog txvgc -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.50.70.91.11.31.51.71.92.12.32.5 txvgc (v) voltage gain (db) upconverter gain vs. txvgc @ -30c upconverter gain vs. txvgc @ 25c upconverter gain vs. txvgc @ 70c
11-281 rf2958 rev a0 050209 pcb design requirements pcb surface finish the pcb surface finish used for rfmd?s qualification process is electroless nickel, immersion gold. typical thickness is 3 inch to 8 inch gold over 180 inch nickel. pcb land pattern recommendation pcb land patterns are based on ipc-sm-782 standards when possible. the pad pattern shown has been developed and tested for optimized assembly at rfmd; however, it may require some modifications to address company specific assembly processes. the pcb land pattern has been developed to accommodate lead and package tolerances. pcb metal land pattern a = 0.69 x 0.28 (mm) typ. b = 0.28 x 0.69 (mm) typ. c = 3.40 (mm) sq. b b b b b b b b pin 1 pin 16 pin 24 pin 32 c a a a a a a a a a a a a a a a a b b b b b b b b 3.50 (mm) typ. 0.50 (mm) typ. 0.50 (mm) typ. 0.63 (mm) typ. 0.63 (mm) typ. 1.75 (mm) typ. 1.75 (mm) typ. 3.50 (mm) typ. figure 1. pcb metal land pattern (top view)
11-282 rf2958 rev a0 050209 pcb solder mask pattern liquid photo-imageable (lpi) solder mask is recommended. th e solder mask footprint will match what is shown for the pcb metal land pattern with a 3mil expansion to accommodate solder mask registration clearance around all pads. the center-grounding pad shall also have a solder mask clearance. expansion of the pads to create solder mask clearance can be provided in the master data or requested from the pcb fabrication supplier. thermal pad and via design the pcb metal land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. thermal vias are required in the pcb layout to effectively conduct heat away from the package. the via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. the via pattern used for the rfmd qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. if micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. a = 0.79 x 0.38 (mm) typ. b = 0.38 x 0.79 (mm) typ. c = 3.55 (mm) sq. b b b b b b b b pin 1 pin 16 pin 24 pin 32 c a a a a a a a a a a a a a a a a b b b b b b b b 3.50 (mm) typ. 0.50 (mm) typ. 0.50 (mm) typ. 0.63 (mm) typ. 0.63 (mm) typ. 1.75 (mm) typ. 1.75 (mm) typ. 3.50 (mm) typ. figure 2. pcb solder mask pattern (top view)

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